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I hope he is on this mail list
The other thing that I considered was the PLL loop filter, having designed a number of PLLs. Bearing in mind that the original AD evaluation board was probably designed to suit a particular requirement, I modified the filter such that a wider range of loop operating conditions could be tried by altering the Phase Detector output current. This current was programmable over a wide range for the ADF4351 and directly influences the loop bandwidth. Now, messing about with surface mount resistors and capacitors is not everybody’s idea of fun and it was not strictly necessary, but it did provide a useful degree of extra tweaking capability. By adjusting the loop bandwidth, it was possible to reduce the impact of spurs (unwanted spurious outputs), whilst maintaining the best possible Phase Noise
I would appreciate to know the datas used for this new loop bandwith filter (nothing on google about G4HIZ tests)
the main reason is to know if we can use such device on THF transverters (2300 up to 24 ghz) as local oscillator
in term of noise, spurs, etc ... stability is another problem ..
I do not remember WHO was working on this subject ...
nb: I hope that my message is in the right place ... otherwise ... sorry
When I first conceived of my Marker Generator (about a year ago) - it was going to be just that - reliable and accurate and to a reasonable quality, but not necessarily too clean. However, I built in the flexibility to allow re-programming to allow it to be used as a test-bed for Fractional and Integer-N PLL investigations. My first objective was to create a marker at 10368.1MHz, using the 3rd harmonic of 3445.033333MHz. This looks like a horrible number, but if you divide the 10MHz reference by 3 to get a phase detector frequency of 3.33333r MHz and multiply by 1036.81 you get the desired output frequency. A Fractional-N PLL was thus envisaged.
When designing a PLL, I set an objective Phase Noise inside the PLL loop bandwidth (in this case it was -80dBc/Hz) to give a reasonable s/n in 2.3kHz bandwidth. In order to reach this, the standard approach is to make the loop bandwidth intersect the phase noise profile at the desired phase noise level (using information provided on the ADF4351 data-sheet).
As concerns the filter mods, I used the black 0.8mm thick PLL boards (from the usual online source) and on programming, found that the loop bandwidth was too small to meet my Phase Noise objective, even at the maximum Phase Detector current (Ipd). Noting that the loop bandwidth is related to Ipd, ie double the current and you should see roughly a 1.8 times increase in loop bandwidth for this board (approximate due to other effects). And so I modified the loop filter for this reason, using component values derived from the Analog Devices AdiSim PLL simulation software, which is freely available for download. The result now is that I can achieve a loop bandwidth of 30kHz at Ipd of 2.81mA but can go up and down to see the effect on spurs.
The spurs in a Fractional-N PLL can be from various sources and indeed whether you care about them depends on your application. For a linear transverter application, spurs are undesirable as they could look like a signal on receive and generate unwanted rubbish on transmit. For a digital system such as for DATV, they may be acceptable, particularly given the wide-band nature of the signal being transmitted. In the ADF4351, spurs can be Fractional, Integer boundary, due to the PFD frequency, or general. For fractional spurs, these can be addressed using the dither function of the device (Low Spur Mode) but this does increase the Phase Noise. Integer Boundary spurs cannot be reduced in this way as they are produced by mixing the multiples of the PFD frequency with the VCO frequency - which are offset due the fractional nature of the PLL. However, both of these spurs can be reduced by the loop filter, if they are outside the loop, as indeed can the PFD frequency spurs, although by design, these should be very low. So we have a trade-off, increase the loop bandwidth to get the desired Phase Noise, or reduce it to reduce the spurs.
My latest iteration of the 10GHz marker did it this way: I used an integer of 1036 and a fraction of not 81/100 but 82/101. As 101 is a prime number, the fractional spurs were much reduced (see data sheet to see how this is possible) leaving these and the integer boundary spurs, which in my case was w/c -41dBc at 100kHz offset with a 30kHz loop BW - not nice, but only a marker don't forget ! The eventual output frequency was 10368.11881MHz, ie with a small offset and Phase Noise was -74dBc at 7kHz offset. Be careful to look out also for general spurs which can appear typically at multiples of the reference frequency. These may arise due to poor PCB design, poor decoupling, etc. I have seen many, but their offset and level generally reduce their significance.
Now for applications in an SHF transverter, surely a fractional PLL isn't necessarily needed and an integer PLL may suffice due to the need for integer MHz ? This is what I have done for 23cm, 13cm and 9cm and achieved very good Phase Noise, exceeding my objective, with no fractional PLL spurs. I have also used the ADF4351 to injection lock my DB6NT 10GHz transverter very nicely using a 103.5MHz input. To use the ADF4351 as an integer PLL, just set the FRAC variable to zero.
Just a couple of points, first, in all cases I have changed the supplied board oscillator for a good quality adjustable TCXO - as detailed in my article. This TCXO has exceeded expectations and is very stable (even at 10GHz) and is calibratable. A second point, I have ignored the subject of Reciprocal Mixing, which may apply additional wide-band Phase Noise constraints for crowded band conditions - not that we see a lot of this on the microwave bands these days !
Incidentally, I have purchased an ADF5355 board from (the late) DG0VE and intend to experiment with this. On the data sheet it looks quite promising.