BATC Forum

Hi there,
I wonder if anyone built this design.
Did it work?
I don't need another SPG, but I wanted to know how this approach to it worked. I am not at all ashamed to admit that I couldn't deduce this from the ciruit diagram; so I built it.
As a construction on Veroboard it didn't work for me. You might say "of course!".
But in trying to find out why, and admittedly clearing up some self inflicted problems, it eventually dawned on me that IC7, a 4040 12 bit counter, only ever has one output high at a time. But in this case it feeds a collection of 3 input and two input AND gates. Unless my understanding of the AND gate has been wrong for over 50 years, none of those gates can do anything!
In this design everything depends upon almost everything else,because it is so interconnected. Hence the only output I get is line sync, at half the correct width.

So if anybody did have this working I would love to know what the answer was.

Thank you ploughing through this.
Tony Jaques
(G3PTD)

By the way, I am thoroughly enjoying myself building some of the comparitively early stuff in CQTV. I can really recommend it.

I don’t know much about the design in question, however the 4040 is a binary counter and so the outputs will sequence through every combination. Your assumption that only one output is high at a time is wrong.

Tony, you may be thinking of the CD4022 / CD4017 Johnson counters, where only one of their 8/10 outputs is high at a time.

Brian

Hello both of you,
And thank you for the replies.
I happen to have the Harris data sheet, but it does agree with several others.
Of course you are quite right that the counter is a binary counter. Indeed it is a ripple-carry binary counter with 12 stages. However the outputs are not binary, or any other, coded output. There are 12 "Q" outputs (1 to 12 or 0 to 11 depending on which data sheet you look at). The author uses 8 of them, and all feeding AND gates. Not only is it evident from the data sheet that each Q output goes high in turn, but that is how it behaves, both in a breadboard layout, and in the EPE digital IC tester. (With all those counts to do it takes over four minutes to do the test!)

Thank You
Tony...

The Q outputs are just the outputs from each stage of the binary counter. They are inherently binary coded.

They will count through every combination from 000000000000 to 111111111111. (Assuming the chip is not reset part way through)

Oh Dear Oh Dear!
I don't mind so much knowing that I can be a bit dim at times, but I do so hate proving it!
You are all correct of course and I do apologise. It is amazing how, when the mind gets stuck on a wrong idea, it persists.
I can't now remember what it was that I did to set me on the wrong track, but I do know that what made it worse was the EPE digital IC tester confirming it for me. Looking at the test code for that revealed that whoever wrote that particular test sequence only read back the results after a count that would send each Q output high. Which of course makes the result look like that of a serial out shift register.
Added to that was that the on board 4040 was permanently reset.
Oh well.
I would still be interested to swap notes with anyone who built the SPG.
In case it is of any interest I have made progress. Following up the permanent reset I found that I had missed a connection that is less that 1/4 inch long on an A4 blowup of the circuit! With that added it is still misbehaving, but it is now probably 90% working instead of 10%.
Perhaps just one more blunder to find and then I can do the real purpose of the whole exercise - finding out just how it works.

Thank you guys.
Tony...

Glad you have made some progress, it sounds like you are getting close.
Making mistakes, finding them, and fixing them is one of the best ways of learning!