Home made FPGA PAL vectorscope
Posted: Wed Oct 15, 2014 11:50 pm
Hi All,
I have been tinkering with some real-time video processing using a DE0-nano FPGA board and a couple of home-made PCBs.
Video codec PCB has 2 x 12 bit ADC and 2 x 14 bit DAC, both running at 25Msps. Card also has anti-alias and reconstruction filters.
User interface card has Ethernet, SD card, 2 x USB, bluetooth etc, but only one of the USB comms ports is used in this video, and connects to a soft-core processor (NIOS II) which manages UI and the digital PLL.
Project started out as an experiment to see how difficult it was to lock a locally generated carrier to colour burst from a PAL video test signal, and as usual everything has got a bit carried away.
Video input is colour bars from a Sony broadcast camera.
Output has a real time monochrome display using a pair of 256 x 256 pixel buffers swapping every frame (ping - pong). Output format video is 312 line progressive at about 50Hz driving a 7" LCD.
All memory is on board the FPGA. Current build uses 31% of available logic elements and 47% of available RAM.
And a short video is here : https://www.youtube.com/watch?v=8o0WLwx-md0
I continue to be amazed what can be done with these NZ$110 FPGA development boards.
From New Zealand in spring time.
-mark
I have been tinkering with some real-time video processing using a DE0-nano FPGA board and a couple of home-made PCBs.
Video codec PCB has 2 x 12 bit ADC and 2 x 14 bit DAC, both running at 25Msps. Card also has anti-alias and reconstruction filters.
User interface card has Ethernet, SD card, 2 x USB, bluetooth etc, but only one of the USB comms ports is used in this video, and connects to a soft-core processor (NIOS II) which manages UI and the digital PLL.
Project started out as an experiment to see how difficult it was to lock a locally generated carrier to colour burst from a PAL video test signal, and as usual everything has got a bit carried away.
Video input is colour bars from a Sony broadcast camera.
Output has a real time monochrome display using a pair of 256 x 256 pixel buffers swapping every frame (ping - pong). Output format video is 312 line progressive at about 50Hz driving a 7" LCD.
All memory is on board the FPGA. Current build uses 31% of available logic elements and 47% of available RAM.
And a short video is here : https://www.youtube.com/watch?v=8o0WLwx-md0
I continue to be amazed what can be done with these NZ$110 FPGA development boards.
From New Zealand in spring time.
-mark