Potential DATV settop box project (aka the Ryde project)

Discussions about the new Ryde "Set-top Box" Style Digital ATV Receiver
YL3AKC
Posts: 41
Joined: Wed Aug 08, 2018 8:42 am

Re: Potential DATV settop box project (aka the Ryde project)

Post by YL3AKC » Mon May 25, 2020 10:49 am

G4GUO wrote:
Mon May 25, 2020 7:47 am
1) is the optimum solution if it can be done (didn't Evariste play about with ARM DMA).
2) Looks like a conventional Minitiouner interface
3) Why add another processor
4) This is a trivial job for an FPGA but adds extra cost (using a CPLD might be a better option)

I suppose it might be possible to use the CSI lanes on a PI to receive the transport stream.

Are we talking about a set top box or a Pi hat now?

- Charles
1) Need to ask Evariste about his experience with DMA.
2) Not exacetly. It is SPI not USB. Made with discrete logic FIFO and parallel-to-serial(SPI) converter.
I had problems on RPI+minitouner+USB+longmynd+HDD recording and with 6.1 MBit/sec. No problem with 2.86 MBit/sec transport streams.
3) MCU act as high speed parallel to SPI converter.
4) Shure, CPLD can do it. You have experience with this and gan make parallel-to-SPI coverter in CPLD. But like with MCU, there is need to program before sale on webshop.

*) To use CSI serial lanes for capturing is much more complex programming and GPU hacking than GPIO.

*) Hat or settop box, it is depending how you look on it. I assume that settop box contain RPi, Serit tuner shield (HAT), PSU, IR, display and cabling.
KA5BBC wrote:
Mon May 25, 2020 10:31 am
I know that I'm a little way out of the normal loop however if this project could be capable of decoding DVB-T / T2, even as a side thought, it may increase the audience for this project in the US (where thete is an inexplicable resistance into DVB-S) and may attract more to the BATC & Portsdown etc.
Well. Receiver is based on Serit DVB-S tuner hardware. It support only DVB-S/S2. DVB-T functionality can be done with official RPi TV-hat or with RTL-SDR USB dongle and (maybe???) some driver hacks to extend frequency range.

Janis, YL3AKC

KA5BBC
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Joined: Thu Jun 28, 2018 6:59 pm

Re: Potential DATV settop box project (aka the Ryde project)

Post by KA5BBC » Mon May 25, 2020 10:57 am

Thanks for the feedback Janis.
Andy, KA5BBC/MM0BQV

g0mjw
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Re: Potential DATV settop box project (aka the Ryde project)

Post by g0mjw » Mon May 25, 2020 11:08 am

Good to see this is looking positive. I don't think we need to determine the physical format for the board just yet. It could be a hat or a standalone board depending mostly on if we are utilising the 40 pin header or not. If we only need a few lines it might be easier and more future proof to go stand-alone.

I wonder if anyone has considered the possibility of using the existing V2 PCB for testing, with a different thing plugging in place of the FTDI module. It would mean we already have the RX hardware. All the signals we need are on that header already, and the 2nd TS can be brought over from its header. A little interface PCB would be easy to make and revise as needed. There should be space for a SN74ALVC7813-25DLR, 74LV165A and a connector, or a dsPIC or even a little FPGA though most are not home construction friendly.

Once the design has settled down a new PCB is probably in order and could include the LNB biasing and both TS.
KA5BBC wrote:
Mon May 25, 2020 10:31 am
I know that I'm a little way out of the normal loop however if this project could be capable of decoding DVB-T / T2, even as a side thought, it may increase the audience for this project in the US (where thete is an inexplicable resistance into DVB-S) and may attract more to the BATC & Portsdown etc.
Not as such no. Sorry the US is out of step still - ironic considering ATSC vs DVB-T. The problem is one of hardware and the tuner we are using being DVB-S/S2. The rest of it though should be the same so it just needs a different tuner, along with all the associated driver software for using it. Not impossible but with no demand outside the US maybe this is something you could research?

Mike

G4GUO
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Re: Potential DATV settop box project (aka the Ryde project)

Post by G4GUO » Mon May 25, 2020 11:30 am

The main issue with DVB-T use in the U.S is that they use non standard channels 2/4 MHz.
We have approached a number (just about every DVB-T chipset manufacturer there are)
but because the volume is so low they won't provide us with enough information to make the
clock changes to get the narrow bandwidths.

We did find one company that would work with us but they were a Taiwanese startup that seem
to have now gone out of buisness.

It might be worth asking Eben Upton to put in a good word with Sony about their chip.

Anyway I digress.

It might be interesting to see if the Minitiouner-Express hardware will work at higher bitrates
It uses a naked FTDI chip (not the module) so the track length betwwen the NIM and the USB
chip are less than 3 cms.

- Charles

YL3AKC
Posts: 41
Joined: Wed Aug 08, 2018 8:42 am

Re: Potential DATV settop box project (aka the Ryde project)

Post by YL3AKC » Mon May 25, 2020 11:32 am

Hello Mike!

Yes, you are right! If SPI will work than it need only small (16 pin???) flat cable.

I am considering to home-etch PCB and connect in parallel with FTDI. Utilize second TS output need to change source code for longmynd software.

Janis, YL3AKC

KA5BBC
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Re: Potential DATV settop box project (aka the Ryde project)

Post by KA5BBC » Mon May 25, 2020 11:50 am

G4GUO wrote:
Mon May 25, 2020 11:30 am
The main issue with DVB-T use in the U.S is that they use non standard channels 2/4 MHz.
That's part of my anti-DVB-T argument here.. they are relying on one single provider for their transmitters (and receivers) who will not be around forever and they have no real alternatives.

I am trying to get pairs of Portsdown and Langstone devices built as quickly as time and budget (plus health and eyesight) will allow so that I can start demonstration at clubs and Hamfests soon.
Andy, KA5BBC/MM0BQV

G4EWJ
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Joined: Wed Feb 17, 2010 10:11 am

Re: Potential DATV settop box project (aka the Ryde project)

Post by G4EWJ » Mon May 25, 2020 1:54 pm

>>OK! GPIO+IRQ is too slow according to Brian. There are many more solutions for this:

I still think the 74HC40105 FIFO approach is worth trying, to find the maximum SR that it would be reliable enough for. You need the HC rather than HCT, as the HCT only works at 5v. RS don't have them and Farnell are out of stock for 7 weeks. Mouser and Digikey have them.

The IDT72* range of FIFOs (available from RS, ~£7) give depths upwards of 256 x 9 bits, but the cheaper ones run at 5v. The input is 3.3v compatible, but the output would need level shifting to 3.3v. It may be possible to synchronise the 2 outputs of the NIM and interleave the data, with the 9th bit indicating which is which.

I don't think there's any easy way of doing DMA from an input port on the RPi. I've seen some output techniques of pacing the DMA with timers, but the NIM is effectively the master device, so I don't know how that approach would work.

Micros can be programmed in circuit and this functionality could be built into the RPi application and be completely transparent to the user. They give maximum flexibility and large buffering capacity at low cost.

Brian

YL3AKC
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Re: Potential DATV settop box project (aka the Ryde project)

Post by YL3AKC » Mon May 25, 2020 2:25 pm

Hello Brian!

DMA, in theory is clocked from NIM, each clock pin rising edge will capture GPIO data, falling edge advance memory pointer. When DMA fill memory, IRQ happen and inform CPU. CPU can copy or allocate new memory buffer for DMA and do other things. I am not confident how to program DMA memory allocation, because there is no example code.

What about max SPI clock on dsPIC? Maybe STM32Fxxx MCU as alternative? I like sn74lv165a SPI solution have more than 55 MBit/sec data rate at 3.3V and seems no special programming on CPU, but need to test it .

For FIFO we need additional GPIO pins to inform CPU that there is data in FIFO and CPU read them while FIFO is empty. SN74ALVC7813 works from 3.3V with 50 MHz (50 MByte/sec) speed. This should be more than enough.

G4EWJ
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Re: Potential DATV settop box project (aka the Ryde project)

Post by G4EWJ » Tue May 26, 2020 12:04 pm

DMA parallel directly into the RPi? I don't think there's a mechanism in the RPi to do that.

Maximum SPI speed is 10-15MHz for the 24/33 series of PICs that I know, so you wouldn't be able to receive broadcast.

The SOIC STM32s look very useful, with 2 SPI ports and a slave mode SPI speed up to 48MHz. Some are cheaper than a 74HC40105. You would need a programming / debugging tool. This one is cheap enough. https://thepihut.com/products/st-link-s ... r-emulator

I'm not sure how the 74LV165A with SPI would work. The RPi would have to provide the clock and it wouldn't know when there was data available to clock out. The NIM can provide a serial bit stream without a parallel to serial converter.

The SN74ALVC78 series are SSOP packages with 0.635mm pin spacing, which I don't think is suitable for homebrew.


Evariste has code on Github for DMA. I've done DMA on bare metal RPi, but it looks a bit more complicated under Linux, so I don't fully understand it yet.

https://github.com/F5OEO/rpidatv


There's a company on Ebay selling the 74HC40105 at £1.57 each for a pair with fastish delivery, which isn't too unreasonable considering what other people are charging.

https://www.ebay.co.uk/itm/152255673865 SOIC
https://www.ebay.co.uk/itm/152255673889 DIP

I think those packages are correct, but check. It doesn't say in the listing.

Is anyone going to have a look at the 74HC40105 solution? I'm still working on a PIC solution, but I can pause that if nobody else is trying the 74HC40105.

Brian

YL3AKC
Posts: 41
Joined: Wed Aug 08, 2018 8:42 am

Re: Potential DATV settop box project (aka the Ryde project)

Post by YL3AKC » Tue May 26, 2020 3:02 pm

Hello Brian!

DMA stuff is good, but need some work and education.

SN74LV165ADR have SOIC version and it cost like 0.3 EUR for small quantities.
So, no problem with this.

RPi must be SPI master and can't accept serial data from NIM directly. That is reason for SN74LV165ADR, and it works with 65 MHz clock or more. That is ~65 MBit/sec transport stream.

FIFO is good to normalize RPI IRQ latency. Yes, you need additional signalling pins (GPIO) between FIFO and RPi to start read data bursts from FIFO to SPI, while NIM send to FIFO with constant rate. Also SN74ALVC7813 have 50 MHz clock. So it is like 400 MBit/sec!!! More than enough Cost 3.2 EUR on small quantities. SSOP package like good old FT232RL. I personally don't have problems to solder it.

I am planning to build SN74ALVC7813 + SN74LV165ADR version. Need to draw schematics, order parts and make PCB. Right now I have too much work on local TV station. That is reason for slow progress.

Keep going with dsPIC version and then try 74HC40105.

Regarding supply for NIM. I see following:
NIM 1.1V and NIM 3.3V digital from DC/DC converter IC similar to RPi. Don't remember name now.
NIM analog 3.3V with linear regulator from 5V rail.
LNB can be built with DC/DC step-up converter with current limiting and voltage select with GPIO pin from RPi. Or that add-on chip what is already built for Minitiouner and have documentation in Wiki. STM LNBH26 is too cool for this project.


PS: What other guys are thinking about it? G4GUO, G8GTZ, G8GKQ?


Janis, YL3AKC

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