1) Need to ask Evariste about his experience with DMA.G4GUO wrote: ↑Mon May 25, 2020 7:47 am1) is the optimum solution if it can be done (didn't Evariste play about with ARM DMA).
2) Looks like a conventional Minitiouner interface
3) Why add another processor
4) This is a trivial job for an FPGA but adds extra cost (using a CPLD might be a better option)
I suppose it might be possible to use the CSI lanes on a PI to receive the transport stream.
Are we talking about a set top box or a Pi hat now?
2) Not exacetly. It is SPI not USB. Made with discrete logic FIFO and parallel-to-serial(SPI) converter.
I had problems on RPI+minitouner+USB+longmynd+HDD recording and with 6.1 MBit/sec. No problem with 2.86 MBit/sec transport streams.
3) MCU act as high speed parallel to SPI converter.
4) Shure, CPLD can do it. You have experience with this and gan make parallel-to-SPI coverter in CPLD. But like with MCU, there is need to program before sale on webshop.
*) To use CSI serial lanes for capturing is much more complex programming and GPU hacking than GPIO.
*) Hat or settop box, it is depending how you look on it. I assume that settop box contain RPi, Serit tuner shield (HAT), PSU, IR, display and cabling.
Well. Receiver is based on Serit DVB-S tuner hardware. It support only DVB-S/S2. DVB-T functionality can be done with official RPi TV-hat or with RTL-SDR USB dongle and (maybe???) some driver hacks to extend frequency range.KA5BBC wrote: ↑Mon May 25, 2020 10:31 amI know that I'm a little way out of the normal loop however if this project could be capable of decoding DVB-T / T2, even as a side thought, it may increase the audience for this project in the US (where thete is an inexplicable resistance into DVB-S) and may attract more to the BATC & Portsdown etc.